This invention relates to computer system architectures and more particularly to a cache memory management system architecture having a high-speed system bus, a very high speed microprocessor interface, a Hardwired Virtual to Real Address Translation lookaside Buffer Unit, and providing for individually determinable by page Cacheable/Non-cacheable selection.
Prior cache memory controllers and memory management systems have been developed along a number of partition lines. Prior art systems have utilized a cache controller, a cache memory, a memory management unit, and translation logic, each as separate partitioned units of the system architecture. In these systems, a CPU which would output an address requesting corresponding data for that address, or preparing to link data to the address corresponding to the output address. A cache controller in conjunction with a separate cache memory and possibly in conjunction with separate memory tables would resolve whether or not the output address corresponded to locations stored within the cache memory. If so, a hit was declared, and the cache controller would coordinate the reading or writing of data to the cache memory via the cache controller. If the data was not present, the cache controller would issue a miss signal back to the CPU. In this case, the prior art systems could either provide for the CPU to coordinate a main memory access to obtain the requested address location data, or the CPU could issue a request to a memory management unit to provide the requested location data. In the case of memory management being utilized, prior art systems provided limited register storage either in the CPU, in the memory management unit, or in main memory to assist in the translation process of virtual to physical address translation.
These prior art systems suffered from several drawbacks. First, due to the physical separation of the various units, overall data throughput rate was reduced because of bus loading and bus delays, and the multiple starting points for access via the cache controller, to the cache memory, or of a miss via the cache controller, cache memory, back to the CPU, to the memory management unit, and to main memory. Secondly, these systems burdened the CPU in the event of a cache miss. Additionally, in order to compensate for the cache controller circuitry in bus delays between the cache controller and cache memory, more expensive higher speed cache memories are required to obtain a cache access cycle time which is not delayed because of the cache controller and bus delay times. Furthermore, translation Of virtual to real addresses required prior initialization and loading of page table directories and page tables, delaying access to Boot memory, mapped Input/Output space, etc.